This invention relates to a capacitor, particularly to a capacitor of large capacitance and low impedance, which is provided in, for example, a high-speed digital circuit and used to bypass a high frequency noise or to prevent the supply voltage from varying.
As electronic apparatus have become smaller and acquired more functions, electronic parts provided therein have been strongly demanded to be smaller and thinner and have a good high frequency characteristic.
Particularly in a high-speed digital circuit of a computer which is required to process a huge amount of information at high speed, clock frequencies are remarkably high even at a personal computer level: 400 MHz to 1 GHz in a CPU chip and 75 MHz to 100 MHz in a bus between chips.
Further, as the integration of LSIs has been enhanced and the number of devices in a chip has increased, there has been an ongoing tendency to reduce the supply voltage in order to suppress power consumption. As these IC circuits have come to process at higher speed and have a higher density and a lower supply voltage, it has become essential for passive parts such as capacitors to have a smaller size, a larger capacity and an excellent characteristics to high frequencies or high-speed pulses.
In order to construct a capacitor of smaller size and larger capacity, it is most effective to reduce the thickness of a dielectric layer tightly held between a pair of electrodes. This thickness reduction is compatible with the aforementioned tendency to decrease the supply voltage.
On the other hand, various problems caused by the high-speed operation of the ICs are more serious than the miniaturization of the respective devices. In the function of the capacitor to remove high-frequency noises, it is particularly important to suppress occurrence of an instantaneous voltage drop which occurs when logic circuits have switched by instantaneously supplying an energy stored in the capacitor (so-called "decoupling capacitor").
The performance required for the decoupling capacitor is to supply a current in response to a current regulation in load more quickly than a clock frequency. Accordingly, this capacitor has to securely fulfill its function in a frequency region of 100 MHz to 1 GHz.
However, the capacitor actually has a resistance and an inductance in addition to a capacitance. The capacitive impedance decreases as the frequency increases, whereas the inductive impedance increases as the frequency increases. Thus, as the operating frequency becomes higher, the inductance of the capacitors restricts a transit current that should be supplied to a logic circuit, thereby causing an instantaneous voltage drop in the logic circuit or a new voltage noise and, as a result, an error in the logic circuit. Particularly, in recent LSIs, the supply voltage decreases to suppress an increase in power consumption due to an increased total number of devices in the logic circuit, and a permissible regulation range of the supply voltage becomes small. Accordingly, in order to suppress the voltage variation range during the high-speed operation to a minimum level, it is very important for the decoupling capacitor to reduce the impedance thereof also in a high-frequency region and to possess a performance of instantaneously supplying the stored electric charges as a necessary current.
A standard for the impedance reduction is to suppress a regulation of 40 mA/ns per driver as disclosed in "Computing Inductive Noise of CMOS Drivers" by A. J. Rainal, IEEE Trans. Comp., Packag., Manufact. Technolo.-Part B, Vol. 19, pp. 789-802 (1996). If a supply voltage is 1.8 V, a permissible range of voltage regulation is 10% of the supply voltage, i.e., 0.18V, and the number of off-chip drivers is 64, an upper limit of inductance is 0.14 nH and impedance at 1 GHz must not exceed about 0.4.OMEGA..
In order to minimize the impedance of the capacitor in a necessary frequency region, the capacitance of the capacitor itself may be increased while the resistance and the inductance of the capacitor are reduced, or the electrostatic capacity may be so reduced as to conform a resonance frequency f0=1/[2.pi.(ESL.multidot.C).sup.1/2 ] determined by an equivalent serial inductance ESL and an electrostatic capacity C to a necessary frequency.
For the electrostatic capacity, the former technique can be most effectively applied by thinning the dielectric layer tightly held between the electrodes as described above. The resistance component is determined by a dielectric loss of the dielectric layer and the resistance of the electrodes. The resistance of the electrodes can be thought to be a substantially constant value apart from a skin effect which becomes eminent in a frequency region above several GHz.
As manners of reducing the inductance, there are a manner of minimizing the length of a current path, a manner of making current paths having loops and minimizing the area of a loop, and a manner of splitting the current path into n paths to reduce the effective inductance to 1/n.
Although attempts have been made to reduce the inductance of the capacitor and the impedance of the capacitors by the above methods, an operable frequency region at an impedance of 0.4.OMEGA. or below is only around the resonance frequency determined by the electrostatic capacity and the inductance of the capacitor. If the capacitor is used by reducing the capacity in a frequency region above the resonance frequency, it can function only in a small range of an order of ten MHz from the resonance frequency.
As a method for realizing a capacitor which functions at a low impedance in a wide frequency region by overcoming the above problem that impedance can be reduced only in a region around the resonance frequency, it may be considered to connect capacitance having different capacities in parallel. For example, an attempt to obtain a capacitor having a large capacitance and an excellent high frequency characteristic by arranging in parallel a plurality of dielectric materials having different dielectric constants is disclosed in Japanese Unexamined Patent Publication No. 6-77083.
For a multi-layer ceramic capacitor, an attempt has been made, as disclosed in Japanese Unexamined Patent Publication No. 8-162368, to develop a noise removing function in a wide frequency region by promoting a low impedance at a resonance point of these two capacitors, with changing the areas of electrodes and the thickness of a dielectric layer in one capacitor, and connecting two capacitors having different capacitances.
Japanese Unexamined Patent Publication No. 9-246098 discloses an attempt to develop a noise removing function in a wide frequency region as above by forming electrodes in the respective layers such that the respective capacities differ from each other and connecting the respective stages in parallel via inductors.
U.S. Pat. No. 5,880,925 discloses a capacitor which including pairs of rectangular electrode plates and rectangular dielectric layer placed between the electrode plates, each rectangular electrode plate having electrode leads on the opposite longer sides. The electrode leads of one of each pair of electrode plates and the electrode leads of the other are alternately arranged on the longer side when viewed above. In this construction, a current from one electrode plate splittingly flows into another electrode. Also, there are formed looped current paths one of which allows the current to flow in a direction opposite to its adjacent looped paths. Accordingly, this capacitor can reduce the inductance.
However, in the thin film capacitor disclosed in Japanese Unexamined Patent Publication No. 6-77083, an equivalent circuit is identical to a single capacitor even if the dielectric layer is divided in a plane while the capacitor has only a pair of terminal electrodes. Thus, only the parallel effect of the dielectric characteristics of the materials, but no effect in the equivalent circuit can be thought to be seen.
The parallel capacitor disclosed in Japanese Unexamined Patent Publication No. 8-162368 is a parallel circuit in the equivalent circuit. However, no large effect by the parallel connection can be obtained if the inductance of the two capacitors in the chip is large. Further, since currents of the same direction flow into the two capacitors in this construction, a mutual inductance of the two capacitors becomes larger. As a result, the effect of the parallel connection cannot be expected.
In the capacitor disclosed in Japanese Unexamined Patent Publication No. 9-246098 in which the inductor is inserted between the parallelly connected capacitors, impedance becomes higher, which results in an undesired increased inductance of the device as a whole. A more critical problem is that a point of maximum impedance due to parallel resonance is present between the respective resonance points and impedance cannot be reduced in a wide frequency region at and above 100 MHz unless this parallel resonance is suppressed.
The capacitor of U.S. Pat. No. 5,880,925, which is provided with electrode leads on the longer sides of an electrode plate, can attain some parallel current paths. Also, this capacitor allows the current to flow in the opposite directions on the adjacent looped paths, thereby reducing the inductance. However, this capacitor does not utilize the electrode plate uniformly. Accordingly, the inductance reduction is not satisfactorily accomplished.